1. Field of the Invention
The present invention relates to a sequence operation processor used to execute a plurality of sequence operations. More specifically, the invention is directed to a sequence operation processor and a sequence operation processing method which employs multi-port RAMs for storing operation data to increase the speed of an operation execution cycle.
2. Description of the Background Art
A sequence processing apparatus, also known as a "programmable logic controller (PLC)," is widely used with machine tools, industrial machines, and the like. The sequence operation processing apparatus executes operations in accordance with a sequence set forth in a program format such as a "ladder program." Such a program is shown in FIG. 10, wherein logical relay contacts X5, X12, and M15 respectively correspond to logical relay coils M13, M6, and Y34 and Y35. Each of the relay coils M13, M6, Y34 and Y35 represents 1-bit data.
In the sequence operation processor, the ladder program is executed by using the following operations:
______________________________________ Instruction Device Processing Time ______________________________________ LD X5 (contact input) t1 OUT M13 (coil output) t1 + t2 LDI X12 (contact input) t1 OUT M6 (coil output) t1 + t2 LDI M15 (contact input) t1 OUT Y34 (coil output) t1 + t2 OUT Y35 (coil output) t1 + t2 ______________________________________
A known sequence operation processor described in Japanese Patent Publication No. 304570/1989 is shown in FIG. 8. As shown in FIG. 8, the sequence operation processor includes a microprocessor 31 for controlling an address decoder 32, a memory 33, and a co-processor 34. The sequence operation processor performs the sequence of operations set forth above in accordance with the timing chart shown in FIG. 9. For example, when the operation of the contact input X5 (instruction LD) is performed, microprocessor 31 outputs a 32-bit instruction word to a first bus 35. As shown in FIG. 8, the seven most significant bits of the 32-bit word designate the co-processor address, the next five significant bits designate the instruction code (e.g., LD, OUT, etc.), the next four significant bits designate the bit location, and the remaining sixteen least significant bits designate the address of the data to be operated on. When the address decoder 32 detects the co-processor address from the instruction word appearing on first bus 35, address decoder 32 outputs a chip select (CS) signal 37 to the co-processor 34, thereby causing the bit location and the instruction code fields to be latched. The co-processor 34 then reads data from memory 33 corresponding to the address field in the instruction word, and executes a bit operation. Similarly, when the coil output operation M13 (instruction OUT) is executed, data read from memory 33 is operated on by the co-processor 34 and the operation result is written into memory 33. In the foregoing description, assuming that t1 is the data read time of the memory 33 and t2 is the data write time, the total time necessary to process the ladder program shown in FIG. 10 is (7.times.t1+4.times.t2).
In order to perform faster processing of a ladder program, Japanese Patent Publication No. 113492/1990 discloses a RAM which allows the data read time t1 to be shortened. This RAM is shown in FIG. 11 and includes a multiplexer 210 for multiplexing an external address bus 222 and an internal address bus 224 to produce an output on a bus 220. The output appearing on bus 220 is stored in a write address register 212 which outputs data on the address bus 224 for input to a multiplexer 214. Multiplexer 214 also selects between external address bus 222 and internal address bus 224 to produce an output on address bus 234. A RAM array 254 receives the output from address bus 234 under control of a write enable signal 230. A comparator 216 is used to compare the address on external address bus 222 with the address on internal address bus 224, and for outputting an address match signal 238 upon detecting a match between the addresses. A multiplexer 250 selects either external data bus 262 or internal data bus 264 under control of chip enable signal 226, thereby providing an output to bus 260. The RAM further includes a write data register 252, a data bus 268 coupled to RAM array 254, and a multiplexer 256 for selecting between data bus 268 and internal data bus 264 depending on the state of the output enable signal 272 and the state of the address match signal 238, thereby providing an output to the external data bus 262.
The operation of the sequence operation processor is similar to the operation described above, except in the instance when the address field in the 32-bit instruction word specified for a new sequence operation is identical to the address field in a preceding sequence operation (e.g., preceding coil output operation). In such a case, the content of the write address register 212 (having been stored during the previous coil output operation) is identical to the content on the external data bus 222 (FIG. 11). Hence, the comparator 216 outputs the address match signal 238, thereby causing the multiplexer 256 to output the information stored in the write data register 252 as output data on internal data bus 264, instead of outputting information stored in RAM array 254 as output data on bus 268. Since the data is read from the write data register 252 rather than from RAM array 254, the data processing of the instruction can be performed in a time t3 which is shorter than the ordinary read time t1 (i.e., the time if the data is read from the RAM array 254). Thus, a coil output operation can be executed in a time (t3+t2) which is shorter than the time (t1+t2). Although the time (t3+t2) achieved by implementing the RAM of FIG. 11 in the sequence operation processor of FIG. 8 is shorter than time (t1+t2), the coil output operation is still limited to the steps of reading data from a memory or a write data register, then executing an operation with the read data, and subsequently writing the operation result back to the memory. Accordingly, such an operation can not be executed in any time shorter than either (t1+t2) or (t3+t2).